The present disclosure relates to semiconductor integrated circuits, and specifically to a semiconductor integrated circuit including an internal power supply circuit configured to generate internal power based on external power to have a power supply voltage different from that of the external power.
In recent years, as semiconductor fabrication technologies have been advanced to provide devices using finer and finer design rules, the integration densities of memories, such as a dynamic random access memory (DRAM) and a static random access memory (SRAM), have been increased. Moreover, as the semiconductor fabrication technologies continue to progress in densification and miniaturization, the voltage of external power supplied to one semiconductor chip, for example, a system-on-chip (hereinafter referred to as SoC) continues to be reduced. Thus, a SoC which operates based on a relatively low power supply voltage has been required.
In a widely known configuration as a SoC on which memories are mounted, an internal power supply circuit mounted in a memory region, specifically an internal boosted power supply block or an internal negative voltage power supply block generates internal power having a relatively high or low power supply voltage based on external power, and the generated internal power is supplied to a memory core. This configuration addresses the problem where direct external supply of a high voltage required in the memory core becomes difficult with decreasing voltage of the external power. Moreover, this configuration aims to increase resistance against variations in power supply voltage inside and outside the SoC. Alternatively, internal power whose power supply voltage is different from that of external power may be supplied to circuit blocks, for example, to processors, and the like other than the memories.
When an internal power supply circuit, for example, an internal boosted power supply block is mounted in a memory region, an external power supply voltage widely varies along with boosting operation, specifically pumping operation, or the like to generate internal power. That is, there has been a problem where so-called power supply noise is generated. The power supply noise of external power influences the operation of other function blocks, and thus is a significant factor of unstable operation of the entirety of the SoC including the memories.
To overcome this problem, it is known to use separate power supply interconnects and power supply terminals, or to insert a filter circuit in a power supply interconnect to reduce the influence of the power supply noise over other function blocks.
For example, in Japanese Patent Publication No. 2000-151376, as illustrated in FIG. 9, in order to reduce the influence of power supply noise of a DC-DC converter 802 including an oscillator circuit 805 performing switching operation at a high speed over the other function block (memory and controlling section 803) to which external power is supplied from an external power supply terminal 804 which also supplies the external power to the DC-DC converter 802, an external power supply interconnect is separated into power supply interconnects 809, 810 respectively of the DC-DC converter 802 and the other function block 803. Resistive elements 811, 812 are respectively inserted in the power supply interconnects 809, 810, thereby reducing high-frequency power supply noise propagating to the other function block 803.
Moreover, for example, Japanese Patent Publication No. 2002-208275 discloses an example in which a resistive element is inserted between an internal power supply circuit mounted in a memory and a mesh-like metal interconnect for supplying internal power generated in the internal power supply circuit onto a function block region of the memory, thereby stably supplying the internal power to a function block of the memory.